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Technology

How Atelier works.

The engineering behind AI-powered chip design exploration.

Architecture, compiler mapping and physical implementation are searched together, every candidate is measured at increasing fidelity on real EDA flows, and every result, good or failed, teaches the engine where to look next.

Open the live demo → Talk to us

01 Position

The AI design exploration engine for specialized silicon.

It sits between your workload and your design flow, and decides what is worth building. Your architects, compiler engineers and EDA tools stay in charge of building it.

notan EDA replacementnotan RTL generatornotan LLM wrapper

02 The loop

One loop from workload to the designs worth taking to implementation.

You bring workloads and constraints. The engine proposes candidates, compiles your models onto each, measures them at increasing fidelity, and learns from every result, good or failed.

01 · DEFINE

Workloads and budget

Model layers or tensor shapes, plus your area, power, latency and process targets. That is the whole input.

in: ONNX / MLIR shapes, PPA budget
02 · EXPLORE

Architecture × compiler

The planner proposes hardware and finds the best compiler mapping for each candidate, across more than a million combinations.

array · dataflow · precision · memory · tiling · loop order
03 · PROVE

Measured, not guessed

Analytical estimates, RTL simulation, synthesis, then place-and-route on your flow, cheapest first. Every result is checked, every failure kept.

milliseconds · seconds · minutes · hours
04 · DELIVER

The designs worth implementing

A Pareto front of designs, each with RTL parameters, its compiler mapping and the evidence behind it. Then the loop learns and runs again.

out: designs, mappings, run history

Adaptive EDA budgeting

The engine decides which candidate deserves expensive EDA time.

Each tier costs orders of magnitude more than the one before it. Instead of a fixed filter, the planner chooses where to spend: a candidate moves on only when it is likely to improve your trade-off, and every result updates that judgement.

Candidates
10,000
Analytical estimatemilliseconds
1,000
RTL simulationseconds
100
Synthesisminutes
20
Place & routehours
5

Illustrative. The actual split is decided per project, from your budget and what the engine learns.

03 Design intelligence

It learns why a design choice moves power, performance and area.

A generic optimizer learns which settings scored well. The engine works across the layers of the stack, runs controlled experiments on its own generators, and keeps every result. Choose a layer to see what it reasons about.

What your models actually need

model→operators→tensor shapes→memory behaviour→compute intensity→hardware needs

Sizing starts from the work, not from last year's chip. Shapes and data reuse decide how large the array should be, how much on-chip memory pays for itself, and which dataflow keeps the multipliers busy.

04 The platform

Four parts that work as one.

Built on standard tools your teams already know: MLIR for the compiler, open or commercial EDA for measurement.

Architecture explorer

Searches the hardware space with the compiler in the loop

Array shape, dataflow, precision, memory hierarchy, banking and implementation settings, each judged by how well your workloads map onto it.

  • systolic arrays
  • weight / output stationary
  • INT8 · INT16
  • SRAM macros
Compiler generator

An MLIR path for every candidate design

Tiling, loop order and memory allocation chosen per architecture, lowered from standard MLIR to the accelerator's own command stream, verified bit-exact on its RTL.

  • linalg
  • transform dialect
  • IREE
  • command ISA
Evaluation fabric

Four fidelity tiers with adaptive budgeting

From millisecond estimates to routed layouts, on-prem or in your cloud account, against open tools or your existing synthesis and place-and-route scripts.

  • analytical model
  • Verilator
  • Yosys · OpenROAD
  • your commercial flow
Design intelligence

Picks the next best experiment

Models where designs fail and why, from timing margins to routing, and chooses the run most likely to move your Pareto front. It improves with every design history it sees.

  • multi-fidelity
  • failure-aware
  • design history

05 Engine architecture

Six stages, one learning loop.

The planner proposes, two generators make it real, the evaluation fabric measures it, and design intelligence turns every result into the next decision.

01Workload models, shapes, PPA budget
02Planner multi-fidelity, failure-aware
03Architecture generator parameterised RTL
04Compiler generator MLIR to command stream
05Evaluation estimate · simulate · synthesize · P&R
06Design intelligence results and failures feed the planner ↺

06 Integrations

Works with the tools your teams already use.

Open tools run in the technical preview today. Commercial flows are connected through your existing scripts during a design-partner engagement, on your machines.

Compiler
  • MLIR
  • IREE
  • linalg
  • transform dialect
Today
Simulation
  • Verilator
  • cocotb
  • NumPy reference
Today
Implementation
  • Yosys
  • OpenROAD
  • ASAP7
Today
Commercial EDA
  • Synopsys
  • Cadence
  • Siemens
  • custom flows
With design partners

07 Where it is going

From one accelerator family to any dataflow accelerator.

Each step widens what the engine can design while keeping the same promise: every recommendation measured, every mapping verified.

Today · technical preview

GEMM accelerators, open flow

  • Parameterised systolic-array generator
  • MLIR compiler path to the command stream
  • Four-tier evaluation on Yosys and OpenROAD
Next · with design partners

Your workloads, your flow

  • Attention and convolution workloads
  • Commercial synthesis and place-and-route
  • Power from simulated switching activity
Then · the platform

Any dataflow accelerator

  • Bring your own RTL generator
  • Design intelligence trained across design histories
  • Compiler bring-up in weeks for new chips

Measured on our technical preview: generated RTL in Verilator, OpenROAD-flow-scripts on the ASAP7 predictive 7 nm kit.

See the engine run on its own output.

Explore every buildable architecture, follow one compile from MLIR to the command stream, and check the estimate against RTL simulation. Or bring your workload and talk to us.

Open the live demo →
hello@zenedgex.in