AI-powered chip design exploration
Design better chips, faster.
Atelier uses AI to explore and optimize chip architectures for your real workloads, across performance, power and area.
Explore more possibilities. Make better architecture decisions. Reduce costly design iterations.
/ Design the chip and its compiler as one.
What if you could explore thousands of chip designs before choosing one?
The problem
Chip design decisions are expensive to change.
The most important hardware decisions are often made early, when the least evidence is available. Architecture, memory, dataflow, precision and software mapping can take months to evaluate, and changing them later means significant engineering effort and costly design iterations.
Atelier brings these decisions into one intelligent design exploration loop.
Explore faster
Evaluate thousands of architecture and implementation possibilities instead of relying on a small number of manual experiments.
Optimize better
Find the best trade-offs across performance, power and area for your actual workloads, not for a generic benchmark.
Reduce design risk
Validate important design decisions earlier, before committing significant engineering resources to implementation.
What makes it different
Hardware and software, designed together.
A chip is only as good as the software that runs on it. Atelier evaluates hardware architectures together with their compiler mappings, so the architecture you select is not just efficient on paper. It is designed around how your workloads will actually execute.
Design the chip and its compiler as one.
Solutions
What can you use Atelier for?
Atelier helps you discover the right architecture to build, and accelerates the journey from workload to chip architecture.
Build a new accelerator
Explore architectures for AI, vision, automotive, robotics, networking and other compute-intensive workloads.
Optimize an existing architecture
Find opportunities to improve performance, power or area without relying only on manual design exploration.
Design workload-specific silicon
Start with your models and workloads and discover architectures optimized for what your chip actually needs to run.
Evaluate architecture choices
Compare compute, memory, dataflow and implementation strategies side by side before committing to one.
Accelerate next-generation chips
Re-run design exploration as workloads and models evolve, instead of restarting the process from scratch.
Bring up the compiler with the hardware
Develop the compiler mapping alongside the architecture, instead of treating compiler enablement as a downstream activity.
How it works
From your workload to optimized designs.
Bring what your chip must run and the limits it must meet. Atelier explores the possibilities and identifies the promising designs to take to implementation.
- Your workloads
- Your requirements
- Optimized designs
- Compiler mappings
- The evidence behind each
Why Atelier
Five reasons the answer is better.
Workload-driven
Design decisions start from the workloads you actually care about.
Hardware + compiler co-design
Architecture and compiler mapping are optimized together.
EDA-grounded
Designs are progressively validated using real implementation flows.
AI-driven exploration
The engine learns from every experiment and focuses computation where it matters.
Design-history intelligence
Every successful and failed experiment adds to the knowledge used next time.
Industries
Built for teams designing silicon.
AI & ML
Accelerators for inference, training and emerging AI workloads.
Automotive & robotics
Specialized compute for perception, autonomy and real-time workloads.
Edge & embedded
Performance and efficiency under tight power and area constraints.
Datacenter & networking
Specialized architectures for high-throughput workloads.
Custom silicon
Workload-specific architectures, without limiting exploration to existing designs.
Results
Evidence, not assumptions.
Measured on the Atelier technical preview. Customer and benchmark results will be published here as they complete.
Generated RTL simulated in Verilator; implementation on OpenROAD-flow-scripts with the ASAP7 predictive 7 nm kit.
Case study
Qwen3 and YOLOv8n, on the RTL.
A whole Qwen3-0.6B token, every matrix multiply bit-exact with its logits equal to the integer reference; and a full object detector, from its quantized model to a generated in-memory computing accelerator: checked on real images, then a whole 640×640 frame run on the generated hardware.
Model: Ultralytics YOLOv8n, INT8. Hardware: one 64×64 digital in-memory-compute engine with a RISC-V (CV32E40P) control core, simulated in Verilator. Implementation: synthesis and floorplan with OpenROAD-flow-scripts on the ASAP7 predictive kit. Next: your foundry. The RTL and design constraints provide a starting point for evaluation in your target foundry flow; technology-specific memories, timing and physical implementation must be revalidated.
Results by workload
The best chip for your targets.
Give us the workload and the area, power and performance it must meet. Atelier searches architecture and compiler together and ranks the candidate designs against every requirement, by what you care about most, with the evidence for each.
Qwen3-0.6B, a whole token
All 645 matrix multiplies of a generated token, 28 layers and the output head, bit-exact on the generated RTL, with the logits equal to the integer reference; the cycle estimate within 0.004% of its 16.8 million cycles.
Transformer matrix multiplies
Compiled through MLIR for 22 accelerator configurations, systolic and in-memory compute, from 4×4 to 128×64. Every program bit-exact against NumPy on the generated RTL; the cycle estimate is a median 1.4% from RTL simulation.
CNN layers
All 63 convolution layers of YOLOv8n, from 3×3 stems to 1×1 heads, compiled onto in-memory-compute engines and run on the generated RTL, bit-exact with the integer reference.
YOLOv8n, end to end
The whole detector on chip: 0.364 mAP50-95 on COCO with the accelerator's integer arithmetic, a full 640×640 frame bit-exact on RTL, and the estimate within 0.05% of its 3.26 million cycles.
Ready to explore your next chip?
Bring your workload, requirements and design constraints. We'll show you what Atelier can discover.