AI-powered chip design exploration
CodeSign Engine uses AI to explore and optimize chip architectures for your real workloads, across performance, power and area.
Explore more possibilities. Make better architecture decisions. Reduce costly design iterations.
/ Design the chip and its compiler as one.
The problem
The most important hardware decisions are often made early, when the least evidence is available. Architecture, memory, dataflow, precision and software mapping can take months to evaluate, and changing them later means significant engineering effort and costly design iterations.
CodeSign brings these decisions into one intelligent design exploration loop.
Evaluate thousands of architecture and implementation possibilities instead of relying on a small number of manual experiments.
Find the best trade-offs across performance, power and area for your actual workloads, not for a generic benchmark.
Validate important design decisions earlier, before committing significant engineering resources to implementation.
What makes it different
A chip is only as good as the software that runs on it. CodeSign evaluates hardware architectures together with their compiler mappings, so the architecture you select is not just efficient on paper. It is designed around how your workloads will actually execute.
Design the chip and its compiler as one.
Solutions
CodeSign helps you discover the right architecture to build, and accelerates the journey from workload to chip architecture.
Explore architectures for AI, vision, automotive, robotics, networking and other compute-intensive workloads.
Find opportunities to improve performance, power or area without relying only on manual design exploration.
Start with your models and workloads and discover architectures optimized for what your chip actually needs to run.
Compare compute, memory, dataflow and implementation strategies side by side before committing to one.
Re-run design exploration as workloads and models evolve, instead of restarting the process from scratch.
Develop the compiler mapping alongside the architecture, instead of treating compiler enablement as a downstream activity.
How it works
Bring what your chip must run and the limits it must meet. CodeSign explores the possibilities and returns the designs worth taking to implementation.
Why CodeSign
Design decisions start from the workloads you actually care about.
Architecture and compiler mapping are optimized together.
Designs are progressively validated using real implementation flows.
The engine learns from every experiment and focuses computation where it matters.
Every successful and failed experiment adds to the knowledge used next time.
Industries
Accelerators for inference, training and emerging AI workloads.
Specialized compute for perception, autonomy and real-time workloads.
Performance and efficiency under tight power and area constraints.
Specialized architectures for high-throughput workloads.
Workload-specific architectures, without limiting exploration to existing designs.
Results
Measured on the CodeSign technical preview. Customer and benchmark results will be published here as they complete.
Generated RTL simulated in Verilator; implementation on OpenROAD-flow-scripts with the ASAP7 predictive 7 nm kit.
Bring your workload, requirements and design constraints. We'll show you what CodeSign can discover.